The present invention relates to a light-driven PNPN switch device and, more particularly, to a PNPN semiconductor switch device free of dV/dt malfunction.
When a surge voltage is applied to a light-driven PNPN switch device, a transient current flows within the device. Due to this current, the device erroneously operates since it has no protective circuit. Such an erroneous operation is called "dV/dt malfunction." There is known a light-driven PNPN switch device formed on a semiconductor chip and provided with a protective circuit against dV/dt malfunction, which is formed on the same chip. A PNPN switch of this type is disclosed in Japanese Patent Publication No. Sho 57-59673. An equivalent circuit of this PNPN switch is shown in FIG. 1 attached hereto.
As shown in FIG. 1, the PNPN switch comprises two PNPN switching elements 10a and 10b. It is driven by the light from a light-emitting diode (LED) 20. Element 10a comprises a P-type anode region 11a, an N-type gate region (substrate) 12a, a P-type gate region 13a and an N-type cathode region 14a. Anode region 11a is coupled to a terminal 1, and cathode region 14a is coupled to a terminal 2. Gate region 13a and cathode region 14a are short-circuited by a resistor 15a. Element 10b has the same structure as element 10a. That is, it comprises a P-type anode region 11b, an N-type gate region 12b (or substrate), a P-type gate region 13b and an N-type cathode region 14b. Anode region 11b and cathode region 14b are connected to terminals 2 and 1. Gate region 13b and cathode region 14b are short-circuited by a resistor 15b.
The PNPN switch includes two error-preventing circuits. First error-preventing circuit comprises an N-type impurity region 21a formed within, and hence short-circuited to, P-type gate region 13a, a MOS gate electrode 22a formed between impurity region 21a and N-type cathode region 14a, two capacitors 23a and 24a coupled in series between anode terminal 1 and P-type gate region 13a, and a resistor 25a coupled in parallel to capacitor 24a. The second error-preventing circuit has the same structure as the first. It comprises an N-type impurity region 21a formed within, and hence short-circuited to, P-type gate region 13a, a MOS gate electrode 22a formed between impurity region 21a and N-type cathode region 14a, two capacitors 23a and 24a connected in series between anode terminal 1 and P-type gate region 13a, and a resistor 25a coupled in parallel to capacitor 24a.
When LED 20 emits light to the PNPN switch while a high voltage and a low voltage are applied to terminals 1 and 2, carriers are generated in the PN junction between N-type region 12a and P-type region 13a which are biased in the opposite directions. As a result, a transient current flows through the PN junction between regions 13a and 14a, thereby forwardly biasing this PN junction. Consequently, PNPN switching element 10a is turned on. Suppose a surge voltage is applied between terminals 1 and 2. Without the error-preventing circuits, a transient current would flow through the PN junction between regions 13a and 14a, thus erroneously turning on PNPN switching element 10a. This does not happen since the error-preventing circuits function in the following manner.
When a surge voltage is applied to terminal 1, it is applied to PNPN switching element 10a, generating a transient current in element 10a, and is applied also to the first error-preventing circuit. In the first error-preventing circuit, the voltage is divided by serially coupled capacitors 23a and 24a into a low voltage. This low voltage is applied to MOS gate electrode 22a. Here it should be noted that capacitors 23a and 24a have such capacitances that the MOS capacitor 24a including MOS gate electrode 22a has a threshold voltage higher than the voltage obtained by dividing the surge voltage. Therefore, when a surge voltage rising fast is applied to terminal 1, an N-type inversion layer (i.e., an N-type channel) is formed in the surface of P-type gate region 13a. The inversion layer electrically connects N-type impurity region 21a to N-type cathode region 14a. As a result, the transient current flows from PNPN switching element 10a, more precisely from the PN junction between N-type region 12a and P-type gate region 13a, to N-type cathode region 14a through N-type impurity region 21a held at the same potential as P-type gate region 13a and through N-type inversion layer formed in the surface of P-type gate region 13a. Since the transient current does not flow through the PN junction between regions 13a and 14a, this PN junction is not biased so much as to turn on PNPN switching element 10a. Hence, a dV/dt malfunction is prevented.
When the surge voltage is relatively low or rises slowly, no N-type inversion layer is formed. In this case, the transient current generated within switching element 10a is small, and the PN junction between regions 13a and 14a is not biased so much as to fire switching element 10a. Hence, no dV/dt malfunction will occur.
FIG. 2 is a plan view of the PNPN switch, and FIG. 3 is a sectional view of the switch, taken along line III--III in FIG. 2.
As shown in FIGS. 2 and 3, an N-type silicon substrate 12 is used, the first half of which is the N-type regions 12a of PNPN switching element 10a and the second half of which is the N-type region 12b of NPNP switching element 10b. As stated above, both elements 10a and 10b have the same structure. Therefore, the structure of only element 10a shown on the left of FIGS. 2 and 3 will be described. P-type anode region 11a and P-type gate region 13a are formed in the surface region of P-type silicon substrate 12, set apart from each other. N-type cathode region 14a and N-type impurity region 21a are formed in the surface region of P-type gate region 13a, set apart from each other. As clearly shown in FIG. 2, a strip 15a equivalent to resistor 15a (FIG. 1) extends from P-type gate region 13a. A thin, patterned silicon oxide layer 31 is formed on the entire surface of substrate 12. A polycrystalline silicon MOS gate electrode 22a is formed on that portion of oxide layer 31 which covers N-type anode region 14a, N-type impurity region 21a and the portion of P-type region 13a located between regions 14a and 21a. A strip 25a equivalent to resistor 25a (FIG. 1) extends from gate electrode 22a. An inter-layer insulation layer 32 of CVD-SiO.sub.2 is formed on the surface of the entire structure. Layer 32 has contact holes. Aluminum electrodes 41a-4a and aluminum lines 45a and 46a are formed on the layer 32. Electrodes 41a and 42a are an anode electrode and a cathode electrode, and extend through the contact holes and are coupled to P-type anode region 11a and N-type cathode region 14a. Electrode 43a is a capacitor electrode formed on that portion of layer 32 which is above MOS gate electrode 22. Electrode 44a extends through the contact hole and is connected to N-type impurity region 21a and P-type gate region 13a, thus short-circuiting regions 13a and 21a. Electrode 44a is also coupled to strip 25a. Anode electrode 41a and capacitor electrode 43a are connected by aluminum line 45a. Aluminum line 46a is coupled to cathode electrode 42a, extends through a contact hole (not shown) cut in layers 31 and 32 and is connected to P-type strip 15a. Hence, line 46a connects electrode 42a to strip 15a (i.e., a diffusion resistor).
Capacitor electrode 43a, MOS gate electrode 22a and the portion of inter-layer insulation layer 32, which is located between electrodes 43a and 22a, constitute capacitor 23a (FIG. 1). MOS gate electrode 22a, silicon substrate 12 and the portion of oxide layer 31, which is located between electrode 22a and substrate 12, form capacitor 24a (FIG. 1).
The PNPN switch device is advantageous in that it can prevent dV/dt malfunction and that its chip area is much smaller than that of the conventional PNPN switch device. However, its breakdown voltage is inevitably low for the following reason.
As evident from FIG. 2, capacitor 23a (FIG. 1) is formed in P-type gate region 13a. Line 45a connecting capacitor electrode 43a and anode electrode 41a unavoidably extends across the reversely biased PN junction between P-type gate region 13a and N-type substrate 12a. When a high, positive surge voltage is applied between terminals 1 and 2, it is directly applied to line 45. Obviously, the surge voltage narrows the depletion layer in the reversely biased PN junction, causing a surface breakdown. The breakdown voltage of the PNPN switch device is therefore lowered.